Lantronix DSTni-EX Manual de usuario

Part Number 900-335 Revision A 3/04 DSTni-EX User Guide Section Five

2 Intended Audience This User Guide is intended for use by hardware and software engineers, programmers, and designers who understand the basic opera

3 Organization This User Guide contains information essential for system architects and design engineers. The information in this User Guide is org

4 22:: SSPPII CCoonnttrroolllleerr This chapter describes the DSTni Serial Peripheral Interface (SPI) controller. Topics include:  Theory of Ope

5 When operating as a slave, the SPI clock signal (SCLK) must be slower than 1/8th of the CPU clock (1/16th is recommended). Note: The SPI is ful

6 SPI Controller Register Definitions SPI_DATA Register SPI_DATA is the SPI Controller Data register. Table 2-2. SPI_DATA Register BIT 15 14 13 12

7 CTL Register CTL is the SPI Controller Control register. Table 2-4. CTL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET

8 SPI_STAT Register To clear a bit in the SPI_STAT register, write a 1 to that bit. Table 2-6. SPI_STAT Register BIT 15 14 13 12 11 10 9 8 7

9 SPI_SSEL Register SPI_SSEL is the Slave Select Bit Count register. Table 2-8. SPI_SSEL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3

10 DVD_CNTR_LO Register DVD_CNTR_LO is the DVD Counter Low Byte register. Table 2-11. DVD_CNTR_LO Register BIT 15 14 13 12 11 10 9 8 7 6 5

11 33:: II22CC CCoonnttrroolllleerr This chapter describes the DSTni I2C controller. Topics include:  Features on page 11  Block Diagram on pa

12 Block Diagram Figure 3-1 shows a block diagram of the DSTni I2C controller. Figure 3-1. DSTni I2C Controller Block Diagram Theory of Operation I2

13 I2C Controller The I2C controller base address is D000h and shares INT2 with the SPI controller. The I2C bus interface requires two bi-directio

14 Table 3-1. Master Transmit Status Codes Code I2C State Microprocessor Response Next I2C Action 18h Addr + W transmitted, ACK received 7-bit ad

15 Servicing the Interrupt After servicing this interrupt, and transmitting the second part of the address, the Status register contains one of the

16 Transmitting Each Data Byte After each data byte transmits, the IFLG is set, and one of the three status codes in Table 3-3 is in the Status regis

17 Table 3-4. Master Receive Status Codes Code I2C State Microprocessor Response Next I2C Action 40h Addr + W transmitted, ACK received 7-bit a

18 Servicing the Interrupt After servicing this interrupt and transmitting the second part of the address, the Status register contains one of the co

19 Receiving Each Data Byte After receiving each data byte, the IFLG is set and one of three status codes in Table 3-6 is in the Status register. W

20 − The IFLG is set and the Status register contains B8h. − After the last transmission byte loads in the Data register, clear

21 Bus Clock Considerations Bus Clock Speed The I2C bus can be defined for bus clock speeds up to 100 Kb/s and up to 400 Kb/s in fast mode. To dete

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22 Resetting the I2C Controller There are two ways to reset the I2C controller.  Using the RSTIN# pin  Writing to the Software Reset register U

23 I2C Controller Register Definitions Slave Address Register Table 3-8. Slave Address Register BIT 7 6 5 4 3 2 1 0 OFFSET D000 EXTENDED ADD

24 Data Register The Data register contains the transmission data/slave address or the receipt data byte.  In transmit mode, the byte is sent most

25 Control Register Table 3-12. Control Register BIT 7 6 5 4 3 2 1 0 OFFSET D004 FIELD IEN ENAB STA STP IFLG AAK /// /// RESET 0 0 0 0

26 Bits Field Name Description 2 AAK Acknowledge 1 = send Acknowledge (LOW level on SDA) during acknowledge clock pulse on the I2C bus if: −Th

27 Table 3-15. Status Register Definitions Bits Field Name Description 7:3 STATUS CODE Status Code Five-bit status code. See Table 3-16. 2:0 ///

28 Clock Control Register The Clock Control register is a Write Only register that contains seven least-significant bits. These least-significant bit

29 Extended Slave Address Register Table 3-19. Extended Slave Address Register BIT 7 6 5 4 3 2 1 0 OFFSET D008 FIELD SLAX7 SLAX6 SLAX5 SLA

30 44:: UUSSBB CCoonnttrroolllleerr This chapter describes the DSTni Universal Serial Bus (USB) controller. Topics include:  Features on page 30

31 Theory of Operation USB Background USB is a serial bus operating at 12 Mb/s. USB provides an expandable, hot-pluggable Plug-and-Play serial inte

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32 Microprocessor Interface The USB microprocessor interface is made up of a slave interface and a master interface.  The slave interface consists

33 Figure 4-1. Buffer Descriptor Table The microprocessor manages buffers intelligently for the USB by updating the BDT as necessary. This allows

34 Table 4-1. USB Data Direction Rx Tx Device OUT or SETUP IN Host IN OUT or SETUP Addressing BDT Entries Before describing how to access end

35 Table 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines… Microprocessor Determines… Who owns the buffer in syst

36 Table 4-6. USB Buffer Descriptor Format Definitions Bits Field Name Description 7 OWN BD Owner Specifies which unit has exclusive access to the

37 USB Transaction When the USB transmits or receives data: 1. The USB uses the address generation in Table 4-5 to compute the BDT address. 2. A

38 USB Register Summary Table 4-7. USB Register Summary Hex Offset Mnemonic Register Description Page 00 INT_STAT Bits for each interrupt source

39 USB Register Definitions The following sections provide the USB register definitions. In these sections:  The register mnemonic is provided fo

40 Bits Field Name Description 8 USB_RST Enable/Disable USB_RST Interrupt 1 = enable the USB_RST interrupt. 0 = disable the USB_RST interrupt (def

41 Error Register The Error register contains bits for each of the error sources in the USB. Each of these bits is qualified with its respective e

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42 Bits Field Name Description 5 DMAERR 1 = USB requests a DMA access to read a new BDT, but is not given the bus before USB needs to receive or

43 Status Register The Status register reports the transaction status within the USB. When the microprocessor has received a TOK_DNE interrupt, the

44 Bits Field Name Description 12 RESET USB Reset Signal 1 = enables the USB to generate USB reset signaling. This allows the USB to reset USB pe

45 Address Register The Address register contains the unique USB address that the USB decodes in peripheral mode (HOST_MODE_EN=0). In host mode (HO

46 Frame Number Registers The Frame Number registers contain the 11-bit frame number. The current frame number is updated in these registers when a S

47 Token Register The Token register performs USB transactions when in host mode (HOST_MODE_EN=1). When the host microprocessor wants to execute a

48 Table 4-18. Token Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0Ah SOF Threshold Register Token Register FIELD CNT[7

49 Endpoint Control Registers The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available on USB for a decoded

50 Table 4-23. Endpoint Control Register Definitions EP_CTL_DIS EP_RX_EN EP_TX_EN Endpoint Enable / Direction Control /// 0 0 Disable endpoint. /

51 Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device

iv Host Mode Operation________________________________________________________ 50 Sample Host Mode Operations _______________________________________

52 Figure 4. Full-Speed Bulk Data Transfers to a Target Device

53 USB Pull-up/Pull-down Resistors USB uses pull-up or pull-down resistors to determine when an attach or detach event occurs on the bus. Host mode

54 USB Interface Signals Clock (CLK) The clock input is required to be connected to a 12 MHz signal that is derived from the USB signals. USP Speed

55 55:: CCAANN CCoonnttrroolllleerrss This chapter describes the DSTni CAN controller. Topics include:  CANBUS Background on page 56  Feature

56 CANBUS Background CAN is a fast and highly reliable, multicast/multimaster, prioritized serial communications protocol that is designed to provide

57 CANBUS Speed and Length Table 7-1 shows the relationship between the bit rate and cable length. Table 5-1. Bit Rates for Different Cable Lengths

58 Theory of Operation The CAN controller appears to the microprocessor as an I/O device. Each peripheral has 256 bytes of I/O address space allocate

59 Hex Offset Register 30 RxMessage: ID, ID28-13 32 ID12-00 34 RxMessage: Data, D55-48, D63-56 36 D39-32, D47-40 38 D23-16, D31-24 3A D07-00,

60 Detailed CAN Register Map Table 5-4. Detailed CAN Register Map Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 TX

61 Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30 RX Msg ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 I

v Table 3-17. Clock Control Register ... 28 Table 3-18. Clo

62 Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x52 Acceptance Mask Register 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

63 CAN Register Definitions TX Message Registers To avoid priority inversion issues in the transmit path, three transmit buffers are available with

64 Tx Message Registers Table 5-5 shows TxMessage_0 registers. The registers for TxMessage_1 and TxMessage_2 are identical except for the offsets. Ta

65 Table 5-12. TxMessage_0:Ctrl Flags BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0E FIELD /// /// /// /// /// /// /// /// //

66 RX Message Registers A 4-message-deep FIFO stores the incoming messages. Status flags indicate how many messages are stored. Additional flags dete

67 Rx Message Registers The following table shows RxMessage registers. See the complete register table at the start of this section. Table 5-14.

68 Table 5-20. Rx Message: Data 39 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 36h FIELD D39 D38 D37 D36 D35 D34 D33 D32 D47

69 Table 5-26. RxMessage: RTR BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 3C FIELD /// AFI_2 AFI_1 AFI_0 /// RTR IDE DLC_3 DLC_

70 Error Count and Status Registers Table 5-30. Tx/Rx Error Count BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 40h FIELD RE7 RE

71 Table 5-34. Tx/Rx Message Level Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 44h FIELD /// RL1 RL0 TL1 TL0 RESET

vi Table 5-34. Tx/Rx Message Level Register ... 71 Table 5-35. Tx/Rx Messa

72 Interrupt Flags The following flags are set on internal events (they activate an interrupt line when enabled). They are cleared by writing a ‘ 1’

73 Interrupt Enable Registers All interrupt sources are grouped into three groups (traffic, error and diagnostics interrupts). To enable a particul

74 Bits Field Name Description 3 OVR_LOAD Overload Condition− int3n group (diagnostic interrupts) 1 = enable flag set. 0 = enable flag not set. 2

75 Figure 5-3. CAN Operating Mode CAN Module 1CAN Module 2acbdCAN Port 1CAN Port 2DSTni Note: The Loopback Mode register in CAN module 2 is not f

76 Table 5-44. Configuration Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 4Eh FIELD OVR_MSG TS2_2 TS2_1 TS2_0 TS1_3 TS1

77 The following relations exist for bit time, time quanta, time segments ½, and the data sampling point. Figure 5-4. Bit Time, Time Quanta, and Sa

78 Acceptance Filter and Acceptance Code Mask Three programmable Acceptance Mask and Acceptance Code register (AMR/ACR) pairs filter incoming message

79 Table 5-50. Acceptance Mask Register: ID 12 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 54h FIELD ID12 ID11 ID10 ID09 ID08

80 Table 5-54. Acceptance Code Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 58h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID2

81 CANbus Analysis Three additional registers are provided for advanced analysis of a CAN system. These registers include arbitration lost and erro

1 11:: AAbboouutt TThhiiss UUsseerr GGuuiiddee This User Guide describes the technical features and programming interfaces of the Lantronix DSTn

82 Error Capture Register The Error Capture register captures the most recent error event with the frame reference pointer, rx- and tx-mode and the a

83 Frame Reference Register The Frame Reference register contains information of the current bit of the CAN message. A frame reference pointer indi

84 Bits Field Name Description 5:0 FRB[5:0] frame_ref_bit_nr A 6-bit vector that counts the bit numbers in one field. Example: if field = “data” =

85 You can also provide local isolated power for the transceiver circuits, as required when using CANopen. If you are using both DeviceNet and CAN

86 Figure 5-8. CAN Transceiver and Isolation Circuits +5_CAN1U6HCPL-O601VCCGND85C670.01ufR1916807+3.3v2R193270CAN_TX34+5_CAN4706RXD4TXDU18PCA82C251CA

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